Determination of Effective Capacitance Area for Pseudo-Transistor based Characterization of bare SOI wafers by Split-C(V) measurements

The split-C(V) technique has served during three decades for independent extraction of the inversion and accumulation charge in MOSFETs from the direct measurement of the gate-to-channel capacitance [1]. The total charge, Q, obtained from the integration of the gateto-channel capacitance curves, can be used for the evaluation of the carrier mobility using the standard MOSFET equations (μ α ID/Q). Recently, the Split-C(V) technique has been applied for the first time to the characterization of carrier mobility in bare SOI wafers using the Pseudo-MOSFET configuration (Figure 1.a). This experimental setup avoids the need for a CMOS processing to obtain mobility vs. inversion charge curves [2-3]. However, there are some particularities associated with the Pseudo-MOSFET configuration when performing split-C(V) measurements that are not present in a regular MOSFET and need to be further investigated: